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| TOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 DESCRIPTION The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and operates from a single 5V supply. Advanced circuit techniques provide both high speed and low power features with a maximum operating current of 5mA/MHz and maximum access time of 100ns/120ns/150ns. When CE2 is a logical low or \CEl is a logical high, the device is placed in low power standby mode in which standby current is 2uA typically. The TC5565APL/AFL has three control inputs. Two chip enable (\CE1, CE2) allow for device selection and data retention control, and an output enable input (\OE) provides fast memory access. Thus the TC5565APL/AFL is suitable for use in various microprocessor application systems where high speed, low power, and battery back up are required. The TC5565APL also features pin compatibility with the 64K bit EPROM (TMM2764D). RAM and EPROM are then interchangeable in the same socket, resulting in flexibility in the definition of the quantity of RAM versus EPROM in microprocessor application systems. The TC5565APL is offered in a dual-in-line 28 pin standard plastic package. The TC5565AFL is offered in 28 pin mini Flat Package. FEATURES Low Power Dissipation 27.5mW/MHz(Max.) operating * Standby Current: 100uA(Max.) Ta=70C * Access Time TC5565APL/AFL-10 : 100ns(Max.) TC5565APL/AFL-12 : 120ns(Max.) TC5565APL/AFL-15 : 150ns(Max.) * 5V Single Power Supply * Power Down Features: CE2, \CE1 * Fully Static Operation Data Retention Supply Voltage: 2.0-5.5V * * * * Directly TTL Compatible and Outputs Pin Compatible with 2764 type EPROM TC5565APL Family (Package Type) : All Inputs Package Type Device Name 600 mil DIP TC5565APL 300 mil DIP *TC5563APL (Slim Package) Flat Package TC5565AFL (SOP) * See TC5563APL Technical Data. BLOCK DIAGRAM PIN CONNECTION (TOP VIEW) AO-A12 R/W \OE \CE1, CE2 I/O1 - I/O8 VDD GND N.C. Address Inputs Read/Write Control Input Output Enable Input Chip Enable Inputs Data Input/Output Power (+5V) Ground No Connection TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 OPERATION MODE \CE1 CE2 \OE R/W 1/01-T/08 POWER Read Write Output Deselect Standby L L L H H H H * L L * H * * H L H * * DOUT DIN High-Z High-Z High-Z IDDO IDDO IDDO IDDS IDDS MAXIMUM RATINGS SYMBOL VDD VIN VI/O PD Tsolder Tstg ITEM Power Supply Voltage Input Voltage Input and Output Voltage Power Dissipation Soldering Temperature RATING -0.3~7.0 *-0.3~7.0 -0-5-VDD+0.5 1.0/0.6** 260-10 -55~150 0-70 UNIT v v v W C sec C C Storage Temperature Topr Operating Temperature * -3.0V at pulse width 50ns MAX. **Flat package D.C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER VDD Power Supply Voltage VIH Input High Voltage VIL VDH Input Low Voltage Data-Retention Supply Voltage MIN. 4.5 2.2 -0.3 2.0 Typ. 5.0 - MAX. 5.5 VDD+0.3 0.8 5.5 UNIT v v V V TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 D.C and OPERATING CHARACTERISTICS (Ta=0~70C, VDD = 5V10%) SYMBOL IIL IOH IOL ILO PARAMETER Input Leakage Current Output High Current Output Low Current Output Leakage Current TEST CONDITION VIN=O~VDD VOH-2-4V VOL-0.4V VIH or CE2-VOL or \CE1 = VIH or CE2=VOL 0r R/W = VIL or \OE=VIH VOUT=0~VDD tcycle =1.0us TC5565APL-10 tcycle TC556SAFL-10 =100ns VDD =5.5V \CE1=VIL CE2=VIH Other input= VIH/VIL MIN. TYP. MAX. UNIT -1.0 4.0 1.0 10 45 1.0 uA mA mA uA mA mA IDDO1 TC5565APL-12 tcycle TC5565AFL-12 =120ns - - 40 mA Operating Current TC5565A?L-15 tcycle TC5565AFL-15 =150ns tcycle=1.0us TC5565APL-10 tcycle =100ns VDD=5.5V \CEl=O.2V CE2=VDD -0.2V Other lnput= VDD - 0.2V/0.2V TC5565AFL-10 TC5565AFL-12 tcycle =120ns TC5565AFL-12 TC5565APL-15 TC5565AFL-15 tcycle =150ns - - 35 mA - - 5 mA - - 40 mA IDD02 - - 35 mA - - 30 3 100 50 mA mA uA uA IDDS1 *IDDS2 Note * Standby Current \Cel = VIH or CE2 = VIL \CE1 = VDD - 0.2V or CE2 = 0.2V VDD = 5.5V VDD = 3.0V 2 1 In standby mode with \CE1>= VDD - 0.2V, these specification limits are guaranteed under the condition of CE2 >= VDD - 0.2V or CE2 <= 0.2V. CAPACITANCE (Ta=25C) SYMBOL PARAMETER Input Capacitance CIN Output Capacitance COUT * This parameter periodically sampled is not 100% tested. TEST CONDITION VIN = GND VOUT = GND MIN. - TYP. - MAX. 10 10 UNIT pF pF TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 A.C. CHARACTERISTICS (Ta=0~70C, VDD = 5V10%) Read Cycle SYMBOL PARAMETER TC5565APL-10 TC5565AFL-10 MIN. MAX. 100 100 100 100 50 10 5 20 35 35 TC5565APL-12 TC5565APL-15 TC5565AFL-12 TC5565AFL-15 MIN. MAX. MIN. MAX 120 150 120 150 120 150 120 150 60 70 10 5 20 40 40 15 5 20 50 50 - tRC tACC tCOL tC02 tOE tCOE tOEE tOD tODO tOH Read Cycle Time Address Access Time \CE1 Access Time CE2 Access Time Output Enable to Output Valid Chip Enable (\CE1, CE2) to Output in Low-Z Output Enable to Output in Low-Z Chip Enable (CE1, CE2) to Output in High-Z Output Enable to Output in High-Z Output Data Hold Time Write Cycle SYMBOL PARAMETER TC5565APL-10 TC5565AFL-10 MIN. MAX. 100 60 80 0 0 35 5 40 0 TC5565APL-12 TC5565APL- 5 TC5565AFL-12 TC5565AFL- 5 MIN. MAX. MIN. MAX.. 120 150 70 90 85 100 0 0 0 0 0 40 50 5 10 50 60 0 0 - Write Cycle Time Write Pulse Width Chip Selection to End of Write tAS Address Set up Time rWR Write Recovery Time tODW R/W to Output High-Z rOEW R/W to Output Low-Z tDS Data Set up Time tDH Data Hold Time A.C. TEST CONDITION Output Load Input Pulse Level Timing Measurement Reference Level tr, tf tWC tWP tCW VIN VOUT : 100pF + 1 TTL Gate : 0.6V, 2.4V : 0.8V, 2.2V : 0.8V, 2.2V : 5ns TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 TIMING WAVEFORMS READ CYCLE (1) WRITE CYCLE 1 (4) (R/W Controlled Write) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 WRITE CYCLE 2 (4) (\CE1 Controlled Write) WRITE CYCLE 3 (4) (CE2 Controlled Write) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 Note 1. R/W is High for Read Cycle. 2. Assuming that \CE1 Low transition of CE2 High transition occurs coincident with or after R/W Low transition, Outputs remain in a high impedance state. Assuming that \CEl High transition or CE2 Low transition occurs coincident with or prior to R/W High transition, Outputs remain in a high impedance state. Assuming that \OE is High for Write Cycle, Outputs are in high impedance state during this period. 3. 4. DATA RETENTION CHARACTERISTICS (Ta=0~70C) SYMBOL VDH IDDS2 PARAMETER Data Retention Supply Voltage Stand by Supply Current VDD=3.0V VDD=5.5V tCDR Chip Deselection to Data Retention Mode tR Recovery Mode Note (1) : Read cycle Time. MIN. 2.0 0 tRC(1) TYP. - MAX. 5.5 50 100 - UNIT V uA us us \CE1 Controlled Data Retention Mode (2) CE2 Controlled Data Retention Mode (4) TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 Note 2 : In \CE1 controlled data retention mode, minimum standby current mode is achieved under the condition Of CE2<= O.2V Or CE2>= VDD -0.2V. If the VIH of \CE1 is 2.2V in operation, IDDS1 current flows during the period that the VDD voltage is going down from 4.5V to 2.4V, In CE2 controlled data retention mode, minimum standby current mode is achieved under the condition of CE2 <= 0.2V. 3: 4; DEVICE INFORMATION The TC5565APL/AFL is an synchronous RAM using address activated circuit technology, thus the internal operation is synchronous. Then once row address change occur, the precharge operation is executed by internal pulse generated from row address transient. Therefore the peak current flows only after row address change, as shown in the following figure. This peak current may induce the noise on VDD /GND lines. Thus the use of about 0.1uF decoupling capacitor for every device is recommended to eliminate such noise. TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15 DIP 28 PIN OUTLINE DRAWING (6D28A-P) Unit in mm Note) Lead pitch is 2.54 and tolerance is +\-0.25 against theoretical center of each lead that is obtained on the basis of No.1 and No.28 leads. MFP 28 PIN OUTLINE DRAWING (F28GC-P) Unit in mm Note) Lead pitch is 1.27 and tolerance is +\-0.12 against theoretical center of each lead that is obtained on the basis of No.1 and N0.28 leads |
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